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2026 will be a massive year for AI hardware, no matter if GPUs, ASICs or beyond.
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And I’m not sure we can still talk about an emerging industry.
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Googles first TPU was released in 2015, over a decade ago and Nvidia will celebrate its 10-year AI anniversary next year.
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Because Volta, the first Tensor Core GPU, launched in 2017. So, it’s settled!
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Not a new industry anymore, but plenty of new chips.
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And that’s what we will take a look at in this video.
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Here are, in no particular order, the most interesting AI chips for 2026.
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Let us know which chip you think will come out on top and leave a comment if we missed a chip, you think deserves to be in the next video.
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Let’s start with a company and a chip that recently announced its first major deployment.
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What was deployed, you ask?
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Three-year-old hardware based on an almost six-year-old architecture.
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I’m talking about Qualcomm finally deploying their AI100 chips at scale.
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Even if the scale was small.
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Installing a cluster of 1,024 AI100 chips doesn’t matter in 2026.
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But what might matter is the new AI200 chip Qualcomm announced in October last year.
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With about 70 billion transistors produced on TSMCs N3E and 768 gigabytes of LowPowerDDR5x memory, the AI200 ASIC is clearly designed for inference.
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Betting on LPDDR5x, instead of the supply constrained HBM, might have been a great idea one year ago, but memory prices are skyrocketing across the board, and that includes LPDDR5x.
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It’s unlikely that AI200 will make major waves this year.
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But its successor AI250 is supposed to come with a new “compute near memory” architecture.
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According to Qualcomm, that results in a 10x increase of effective memory bandwidth.
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Paired with fast next-gen LPDDR6 memory, there might be something worthwhile on the horizon.
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So don’t put on your party hats just yet, but do keep Qualcomm in mind.
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If Nvidia is Goliath, this company would be David.
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At least I’m sure that’s what AMD would like to hear.
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AMD is the second major player in the GPU space and 2026 could be a turning point.
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If MI455X and the Helios rack are on time.
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MI455X is based on the new CDNA 5 architecture and packs 320 billion transistors into a mix of twelve 2nm and 3nm logic chiplets, connected via advanced 3. 5D packaging.
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But the biggest selling point could be the massive memory setup.
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MI455X comes with 432 gigabytes of next-gen HBM4 and with a bandwidth of almost 20 terabytes per second.
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There’s much more to MI455X and the Helios rack than we have time for in this video.
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If you want to know how AMD is challenging Nvidia, check out the SemiAnalysis article on AMD’s AI strategy.
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It not only offers a deep-dive into MI455X, but also explains the Helios rack architecture.
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It’s definitely worth a read; I’ll drop a link in the video description below.
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Google is truly the grandfather of AI.
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Not only was “Attention is all you need” basically a Google paper, but TPUs have been kicking it since 2015.
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While everyone was hyped about blockchains, Google already prepared for AI.
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Ironwood, aka TPUv7, is built on TSMCs N3E with very likely over 100 billion transistors across two large compute chiplets and comes with 192 gigabytes of HBM3e.
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It’s specifically designed to run Gemini inference.
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But Goole’s superpowers are the so-called Optical Circuit Switches.
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These are tiny physical mirrors that allow for a fast and super-efficient optical interconnect.
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Google uses them to create “Superpods” that connect up to 9,216 TPUs.
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My further reading recommendation is, as usual, the SemiAnalysis TPUv7 deep-dive.
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TPUs offer a whole different approach to AI workloads and have a very different TCO metric.
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Link in the description below.
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TPUs always have been at the forefront, but so far, they were only used by Google.
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This changes with Ironwood.
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The question is, if external customers can use them as well as Google can.
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If so, Ironwood will be a heavyweight for efficient and low-cost inference.
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Another chip that isn’t really brand new, but still hot for 2026, is Cerebras Wafer Scale Engine 3 or WSE-3.
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It was launched back in 2024, but new clusters have just recently been announced.
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WSE-3, as the name implies, uses an entire silicon wafer to create a massive chip.
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It contains an unimaginable amount of SRAM.
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No, not megabytes, I’m talking about 44 gigabytes.
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And a theoretical memory bandwidth of 21 petabytes per second.
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But remember, we are talking about an entire wafer.
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Based on the slightly older N4P node, it contains a whopping 4 trillion transistors.
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Everything is extraordinary with WSE-3.
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But in 2026, 44 gigabytes aren’t really cutting it anymore. Even if it’s SRAM.
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Still, a very unique concept and competitive when it comes to super-fast service.
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While WSE-3 could be the odd one out in 2026, we might see an announcement of WSE-4. Fingers crossed.
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Groq is an interesting one.
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Not to be confused with Elon Musks Grok AI model.
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The one I’m talking about has a q, not a k.
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And that Groq with q got acquired by Nvidia.
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We don’t know for sure if there will be a 2026 product or if it’s more of a foundation for the future.
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But I still wanted to mention it, because it’s a very cool concept.
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The Groq Language Processing Unit, or LPU for short, has relatively unspectacular specs.
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55 billion transistors on a 14nm GlobalFoundry node.
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And no external memory at all.
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Nothing to write home about it seems.
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But the LPU doesn’t need any of that.
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It has 230 megabytes of ultra-fast SRAM placed super close to the compute cores.
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The chip is designed in a way that every step, every calculation, runs like clockwork.
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This is called deterministic execution and it basically eliminates the latency problems that GPUs have to deal with.
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But because you have so little memory, you need to connect a lot of LPUs to run even smaller models.
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Everything is a trade-off.
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No matter what, Nvidia thought it was worth about $20 billion dollars.
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And I’m excited to see what the 2nd gen LPU, based on Samsungs 4nm process, can do.
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And what Nvidia does with it.
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Ok, I can’t avoid the elephant in the room any longer.
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Nvidia is number one for a reason.
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And with Vera-Rubin, Nvidia is taking the next step, moving to TSMCs N3P and HBM4.
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A single VR200 can crank out an insane 35 petaflops of FP4 per package.
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Combined with 288 gigabytes of ultra-fast HBM4 at 22 terabytes per second of bandwidth, at least that’s the speed Nvidia is targeting, a single Superchip is already a force to be reckoned with.
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But combining 72 of these in the NVL72 rack, using Nvidia’s exquisite NVLink scale-up network, Vera-Rubin will very likely once again top the charts. Or will it?
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MI455X does have a memory advantage.
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At least until Rubin Ultra, which will come with a clean terabyte of HBM.
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No matter what, there’s no doubt that VR200 is the most anticipated release for 2026.
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And it’s also the topic of the latest SemiAnalysis article, just in case you really want to know how Vera-Rubin is built and how it works.
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Mark Zuckerberg is on a massive spending spree.
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Meta is basically buying everything they can and that includes GPUs from Nvidia and AMD and even TPUs from Google.
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Which makes it easy to forget that Meta has its own silicon.
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The Meta Training and Inference Accelerator, MTIA for short, is now in its third iteration.
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We don’t know all the specs yet, but it will be produced in TSMCs N3P with very likely over 100 billion transistors and HBM memory.
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Previous MTIA version still used LPDDR5x.
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Meta knows exactly what their internal workload needs.
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And that’s not only AI chatbots, but AI recommendation models that run the algorithms for Facebook, Instagram and Threads.
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MTIAv3 won’t be Metas chip for AGI, but it offers good margins for their business model.
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And that means, they can use all the external hardware to train new models, while internally they switch to their own silicon for inference.
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Looking at the roadmap, we will see a lot more MTIA in the future.
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There is a lot of AI silicon, but only a few chips see truly large-scale deployment.
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One of them is Amazon’s Trainium.
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There are hundreds of thousands of Trainium2 chips deployed inside the AWS AI datacenters in Canton and New Carlisle.
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Which makes Trainium3 a top contender for future large-scale deployment.
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Trainium3, despite its name, combines training and inference capabilities in a single chip.
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Built on TSMCs N3P, it consists of about 125 billion transistors and comes with 144 gigabytes of fast HBM3e.
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You can find much more, including TCO numbers, in the SemiAnalysis Trainium3 deep-dive.
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And yes, it’s an actual technical deep-dive.
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Anthropic’s amazing Claude Code was trained and runs on Trainium, it can only get better with Trainium3.
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And Anthropic isn’t the only fan.
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OpenAI will use 2 gigawatts of Trainium compute starting this year.
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If you are looking for an ASIC with truly large-scale deployment, look no further than Trainium3.
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Microsoft’s first ASIC, Maia 100, was a little bit of a mystery.
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Like every new in-house design, it has to prove itself first.
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Does it warrant a second generation?
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With Maia 200 we have the answer.
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At around 825 square millimeters, the almost reticle busting chip contains 140 billion transistors, is manufactured in TSMCs N3P and comes with a pretty large 216 gigabytes of HBM3e.
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Maia 200 will be used for inference and is optimized for FP8 and FP4, providing over 5 and 10 petaflops respectively.
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Microsoft will use it for its in-house models but Maia 200 will also run future ChatGPT models.
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More and more inference is moving away from Nvidia to custom silicon.
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Last, but certainly not least, we have Intel, who is having another go at an AI GPU.
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But it doesn’t seem like Jaguar Shores is targeting a 2026 release.
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But with so many ASICs, I had to talk about one more GPU, even if it might be a 2027 product.
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Jaguar Shores comes with a pretty strong spec sheet.
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18A process node, 175 billion transistors and 288 gigabytes of HBM4.
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On paper, it's competitive. But paper is patient.
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After many attempts, Intel not only has to prove it can build and produce an AI GPU, but also provide the proper software support.
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But no matter what, a third player in the GPU space would be very welcome.
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And Jaguar Shore will show if Intel can compete again.
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The chip wars are heating up and what we just talked about is only a small selection of the entire market.
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If you compare this list with what the SemiAnalysis Accelerator & HBM model tracks, you will know what I mean.
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Right now, all lines are only going up. But for how long?
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If you are working in or with the industry and are interested in a clear picture view of the entire AI silicon market and where it’s headed, the SemiAnalysis Accelerator & HBM model is your best choice.
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Not only does it offer a comprehensive overview of all current and future chips, it also provides shipment numbers and ASPs.
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Plus, deep insights into the HBM market.
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You can find the link in the description below.
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Right next to all the deep-dive articles we talked about in the video.
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And if you are less interested in spec, but more in real-world performance, InferenceX offers comprehensive benchmarks across a wide range of accelerators.
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Because what really matters in the end is how a chip performs.
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Check out the SemiAnalysis InferenceX dashboard, it’s free.
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You know where you can find the link.
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I hope you enjoyed this video and see you in the next one!